Skip to content

MAC Unit — Plan

Single 4-bit x 4-bit sequential shift-add multiplier feeding a 12-bit accumulator. Real 74xx TTL logic on breadboard. No FPGA, no EEPROM/array-auto-walk (that is a separate future phase, deliberately excluded here to keep this build finishable).

Manual operation: you key in one (a, b) pair via DIP switches, trigger a multiply, result adds into the accumulator. Repeat by hand for multiple pairs (this is how you do a dot product / "array multiply" manually — see study.md).

1. Final architecture

  • Multiplicand M: 4-bit, static per operation
  • Multiplier Q: 4-bit, shifts right once per cycle
  • Partial product A: 4-bit, shifts right together with Q as one 9-bit unit {C,A,Q}
  • 4 clock cycles per multiply (one per bit of Q)
  • Result after 4 cycles: 8-bit product in {A,Q}
  • Accumulator: 12-bit, holds running total across multiple MAC operations (12 bits chosen for headroom: 4-term dot product worst case = 4 x 15 x 15 = 900, needs >= 10 bits, rounded to 12 to match clean 4+8 bit chip boundaries)

2. Full component list

Qty Part Role
1 74LS175 M register — holds multiplicand, loaded once
1 74LS175 A register — holds partial product, updates every cycle
1 74LS194 Q register — 4-bit universal shift register, shift-right mode
1 74LS283 4-bit adder — computes A + M each cycle
1 74LS157 Quad 2:1 mux — selects (A+M) vs unchanged A based on Q's LSB
1 74LS08 Quad AND gate (1 of 4 gates used) — gates carry-out by Q's LSB
1 74LS164 8-bit serial-in shift register, wired as ring counter — sequences the 4 cycles
3 74LS283 Chained 4-bit adders — 12-bit adder for accumulator stage
1 74LS273 Accumulator register, lower 8 bits
1 74LS175 Accumulator register, upper 4 bits
1 NE555 Astable clock source
1 74LS14 Hex Schmitt-trigger inverter — debounce manual step button, clean edges

Total ICs: 13

3. Supporting components

  • DIP switches: 8 total (4 for M input, 4 for Q input)
  • LEDs: 8 (A+Q / product bits) + 12 (accumulator bits) + 4 (ring counter state) = 24
  • Resistors: 330-470 ohm per LED; 10k ohm pull-downs on every switch input
  • Capacitors: 0.1uF ceramic decoupling near every 2-3 ICs (non-negotiable); timing resistor/capacitor for 555 astable (values depend on target clock speed, pick slow — 1-2 Hz — for visual debugging, add a speed-up option later)
  • Power: regulated 5V. Either bench supply, or 7805 regulator fed from 9V, with input/output capacitors per 7805 datasheet
  • Breadboards: expect to need 2-3 full-size boards
  • Logic probe or multimeter for debugging (a scope is nice-to-have, not required)

4. Build order — do not skip or reorder

Phase 0: Clock + debounce

  • Build 555 astable clock alone
  • Build 74LS14-based pushbutton debounce for manual single-step
  • Verify both independently (LED blink for clock, clean single pulse per press for debounce) before connecting anything else

Phase 1: Combinational core

  • Wire M register, A register, 74LS283 adder, 74LS157 mux
  • No sequencing yet — set static inputs on switches, manually check Sum and Carry outputs against hand-computed values
  • Confirms the adder + mux logic is correct in isolation

Phase 2: Sequencing

  • Add Q shift register (74LS194) and ring counter (74LS164)
  • Wire the full {C,A,Q} 9-bit shift-right-per-cycle datapath
  • Run one full 4-cycle multiply, compare final {A,Q} against hand-computed test vectors (section 5)

Phase 3: Accumulator

  • Add the 3x chained 74LS283 (12-bit adder), 74LS273 + 74LS175 (accumulator regs)
  • Run the full 4-term MAC test (section 5)

5. Test vectors — compute by hand before building, verify after

Multiply-only

  • 0000 x 1111 = 00000000 (zero case)
  • 1111 x 1111 = 11100001 (225, max value, full carry chain)
  • 1010 x 0101 = 00110010 (50)
  • 0001 x 0001 = 00000001 (identity)

Full MAC / 4-term dot product (run sequentially, accumulator grows)

  1. 3 x 3 = 9 -> accumulator = 9
  2. 5 x 4 = 20 -> accumulator = 29
  3. 2 x 7 = 14 -> accumulator = 43
  4. 15 x 15 = 225 -> accumulator = 268 (binary: 000100001100)

Step 4 deliberately forces a large carry into the accumulator chain — if the 12-bit adder chaining is wired wrong, this is where it will surface.

6. Operating it on an "array" (manual dot product)

No memory, no auto-walk — this is a deliberate scope cut (EEPROM + address counter + comparator phase is cut entirely, too much cost/complexity for this build). To do a dot product of two arrays by hand:

  1. Set switches to array1[0], array2[0]
  2. Trigger multiply (let ring counter run its 4 cycles)
  3. Accumulator now holds the running sum
  4. Set switches to next pair, trigger again
  5. Repeat for each pair
  6. Read final accumulator value after the last pair

Practical limit: 4-8 term dot products are reasonable to key in and demo by hand. This is honest and should be described as "single MAC unit, sequentially operated" — not a parallel accelerator. That distinction matters for accuracy when posting about it.

7. Debugging checklist (in order of most common breadboard failure)

  1. Power/ground — check decoupling caps are present, check for cold joints or loose jumpers on rails first, before assuming logic error
  2. Clock — verify clean single edges on scope/LED before trusting anything downstream
  3. Combinational stage (Phase 1) — re-verify with static inputs if sequencing breaks
  4. Ring counter — confirm exactly one LED lit at a time, walking correctly, 4 positions, wrapping/stopping correctly
  5. Compare intermediate A/Q values at each cycle against the hand-worked 1010 x 0101 example in study.md — this catches datapath wiring errors precisely

8. Explicit non-goals for this build

  • No array/EEPROM auto-sequencing (cut for cost/complexity — noted above)
  • No parallel MAC array (that is the future mini-npu / systolic array project, separate build, comes after seatorch produces real trained weights)
  • No claim of "AI accelerator" — this is a single MAC datapath, framed honestly