Mini NPU — study

Digital design and computer architecture concepts only — the ML side is seatorch's job, not duplicated here.

Before milestone 1–2 (gates, FSMs, MAC)

• HDLBits — work through gates, FSMs, counters before writing the MAC unit
• Yosys manual — skim now, reference later during synthesis

Before milestone 4–5 (systolic array, controller, BRAM)

• MIT 6.004 — Computation Structures — lectures 15–18, memory hierarchy and datapath design
• Re-read the systolic array section of the original Mini NPU brainstorm doc before starting milestone 4 — the dataflow diagram (weights horizontal, activations vertical, partial sums flowing) is the thing to internalize before writing any PE code

Before milestone 6–7 (UART)

• No dedicated reading — UART is simple enough to implement from the protocol spec directly (start bit, 8 data bits, stop bit, fixed baud rate). Look up "UART protocol basics" only if the framing logic isn't clear from a first attempt.

Before milestone 10 (quantization import)

• Nothing new — this consumes seatorch's study.md quantization section. The NPU side is just "read the .hex format correctly," not new ML theory.

Before milestone 12 (benchmarking)

• No new material — apply the same profiling instinct from seatorch's SIMD/cache work (Siboehm's CPU article) to reading LUT/BRAM/DSP utilization reports from the Gowin toolchain.